| 000 -LEADER |
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| fixed length control field |
04398nam a2200205Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
200103s 2013 ||||xx |||||||||||||| ||und|| |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9788131794746 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.395 |
| Item number |
MAN |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Mano, M. Morris |
| 245 #0 - TITLE STATEMENT |
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| Title |
Digital design with an introduction to the verilog HDL |
| 250 ## - EDITION STATEMENT |
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| Edition statement |
5th |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Name of publisher, distributor, etc |
Dorling Kindersley (India) Pvt. Ltd. |
| Date of publication, distribution, etc |
2013 |
| Place of publication, distribution, etc |
India |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
xv, 678p. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
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| Bibliography, etc |
1 Digital Systems and Binary Numbers <br/> 1.1 Digital Systems <br/> 1.2 Binary Numbers <br/> 1.3 Number‐Base Conversions <br/> 1.4 Octal and Hexadecimal Numbers <br/> 1.5 Complements of Numbers <br/> 1.6 Signed Binary Numbers <br/> 1.7 Binary Codes<br/> 1.8 Binary Storage and Registers <br/> 1.9 Binary Logic <br/>2 Boolean Algebra and Logic Gates <br/> 2.1 Introduction <br/> 2.2 Basic Definitions <br/> 2.3 Axiomatic Definition of Boolean Algebra <br/> 2.4 Basic Theorems and Properties of Boolean Algebra <br/> 2.5 Boolean Functions <br/> 2.6 Canonical and Standard Forms <br/> 2.7 Other Logic Operations <br/> 2.8 Digital Logic Gates <br/> 2.9 Integrated Circuits <br/>3 G a t e ‐ L e v e l Minimization <br/> 3.1 Introduction <br/> 3.2 The Map Method <br/> 3.3 Four‐Variable K-Map <br/> 3.4 Product‐of‐Sums Simplification <br/> 3.5 Don’t‐Care Conditions <br/> 3.6 NAND and NOR Implementation <br/> 3.7 Other Two‐Level Implementations <br/> 3.8 Exclusive‐OR Function <br/> 3.9 Hardware Description Language <br/>4 Combinational Logic <br/> 4.1 Introduction <br/> 4.2 Combinational Circuits <br/> 4.3 Analysis Procedure <br/> 4.4 Design Procedure <br/> 4.5 Binary Adder‐Subtractor<br/> 4.6 Decimal Adder <br/> 4.7 Binary Multiplier <br/> 4.8 Magnitude Comparator <br/> 4.9 Decoders <br/> 4.10 Encoders <br/> 4.11 Multiplexers <br/> 4.12 HDL Models of Combinational Circuits<br/>5 S y n c h r o n o u s S e q u e n t i a l L o g i c <br/> 5.1 Introduction <br/> 5.2 Sequential Circuits <br/> 5.3 Storage Elements: Latches <br/> 5.4 Storage Elements: Flip‐Flops <br/> 5.5 Analysis of Clocked Sequential Circuits <br/> 5.6 Synthesizable HDL Models of Sequential Circuits <br/> 5.7 State Reduction and Assignment<br/> 5.8 Design Procedure <br/>6 R e g i s t e r s a n d C o u n t e r s <br/> 6.1 Registers <br/> 6.2 Shift Registers <br/> 6.3 Ripple Counters <br/> 6.4 Synchronous Counters <br/> 6.5 Other Counters <br/> 6.6 HDL for Registers and Counter<br/>7 Memory and Programmable Logic <br/> 7.1 Introduction <br/> 7.2 Random‐Access Memory <br/> 7.3 Memory Decoding <br/> 7.4 Error Detection and Correction <br/> 7.5 Read‐Only Memory <br/> 7.6 Programmable Logic Array <br/> 7.7 Programmable Array Logic <br/> 7.8 Sequential Programmable Devices <br/>8 Designatthe Register Transfer Level <br/> 8.1 Introduction <br/> 8.2 Register Transfer Level Notation <br/> 8.3 Register Transfer Level in HDL <br/> 8.4 Algorithmic State Machines (ASMs) <br/> 8.5 Design Example (ASMD CHART) <br/> 8.6 HDL Description of Design Example <br/> 8.7 Sequential Binary Multiplier <br/> 8.8 Control Logic <br/> 8.9 HDL Description of Binary Multiplier <br/> 8.10 Design with Multiplexers <br/> 8.11 Race‐Free Design (Software Race Conditions) <br/> 8.12 Latch‐Free Design (Why Waste Silicon?) <br/> 8.13 Other Language Features <br/>9 L a b o r a t o r y E x p e r i m e n t s<br/>with Standard ICs and FPGAs <br/> 9.1 Introduction to Experiments <br/> 9.2 Experiment 1: Binary and Decimal Numbers <br/> 9.3 Experiment 2: Digital Logic Gates<br/> 9.4 Experiment 3: Simplification of Boolean Functions <br/> 9.5 Experiment 4: Combinational Circuits <br/> 9.6 Experiment 5: Code Converters <br/> 9.7 Experiment 6: Design with Multiplexers <br/> 9.8 Experiment 7: Adders and Subtractors <br/> 9.9 Experiment 8: Flip‐Flops <br/> 9.10 Experiment 9: Sequential Circuits <br/> 9.11 Experiment 10: Counters <br/> 9.12 Experiment 11: Shift Registers <br/> 9.13 Experiment 12: Serial Addition <br/> 9.14 Experiment 13: Memory Unit <br/> 9.15 Experiment 14: Lamp Handball <br/> 9.16 Experiment 15: Clock‐Pulse Generator <br/> 9.17 Experiment 16: Parallel Adder and Accumulator <br/> 9.18 Experiment 17: Binary Multiplier <br/> 9.19 Verilog HDL Simulation Experiments<br/>and Rapid Prototyping with FPGAs <br/>1 0 Standard Graphic Symbols <br/> 10.1 Rectangular‐Shape Symbols<br/> 10.2 Qualifying Symbols <br/> 10.3 Dependency Notation <br/> 10.4 Symbols for Combinational Elements <br/> 10.5 Symbols for Flip‐Flops <br/> 10.6 Symbols for Registers <br/> 10.7 Symbols for Counters <br/> 10.8 Symbol for RAM <br/> |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Boolean Algebra and Logic Gates |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Memory and programmable Logic |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Asynchronous Sequential Logic |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Ciletti, Michael D. |
| Relator term |
Co-author |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Item type |
Books |
